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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i2srx___config.html">XI2srx_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the XI2s Receiver.  <a href="struct_x_i2srx___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The XI2s Receiver driver instance data.  <a href="struct_x_i2s___rx.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i2s___rx___log_item.html">XI2s_Rx_LogItem</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This structure is used to store log events.  <a href="struct_x_i2s___rx___log_item.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i2s___rx___log.html">XI2s_Rx_Log</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The XI2s Receiver Log buffer.  <a href="struct_x_i2s___rx___log.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga7b7e72e5a3a6b2d4cbddf5f41545c574"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga7b7e72e5a3a6b2d4cbddf5f41545c574">XI2s_Rx_GetMaxChannels</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga7b7e72e5a3a6b2d4cbddf5f41545c574"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the maximum number of XI2s channels available.  <a href="#ga7b7e72e5a3a6b2d4cbddf5f41545c574">More...</a><br/></td></tr>
<tr class="separator:ga7b7e72e5a3a6b2d4cbddf5f41545c574"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf7ee99ef4ef8a11b48c8da71da0398b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gadf7ee99ef4ef8a11b48c8da71da0398b">XI2s_Rx_IsXI2sMaster</a>(InstancePtr)</td></tr>
<tr class="memdesc:gadf7ee99ef4ef8a11b48c8da71da0398b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the XI2s operating mode.  <a href="#gadf7ee99ef4ef8a11b48c8da71da0398b">More...</a><br/></td></tr>
<tr class="separator:gadf7ee99ef4ef8a11b48c8da71da0398b"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:gaef13cc9c4d09dc05e1027c43bc2aeed2"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaef13cc9c4d09dc05e1027c43bc2aeed2">XI2s_Rx_Callback</a> )(void *CallbackRef)</td></tr>
<tr class="memdesc:gaef13cc9c4d09dc05e1027c43bc2aeed2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Callback function data type for handling interrupt requests from the XI2s Receiver peripheral.  <a href="#gaef13cc9c4d09dc05e1027c43bc2aeed2">More...</a><br/></td></tr>
<tr class="separator:gaef13cc9c4d09dc05e1027c43bc2aeed2"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:gace941535376f24ef90b44f160f55b70e"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gace941535376f24ef90b44f160f55b70e">XI2s_Rx_ChMuxInput</a> { <br/>
&#160;&#160;<a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70eaabeb21056fc06cd622d7a0b191a0127e">XI2S_RX_CHMUX_DISABLED</a> = 0, 
<a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea0df7f22d4a2d5f2f1dbf9305443194e1">XI2S_RX_CHMUX_XI2S_01</a>, 
<a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea269c4b47b2a78c065aee963d3396aab2">XI2S_RX_CHMUX_XI2S_23</a>, 
<a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea55bc0f78e50439c70f6a2580471a4b3b">XI2S_RX_CHMUX_XI2S_45</a>, 
<br/>
&#160;&#160;<a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea51c18d250475c4f196015e8972e44b1f">XI2S_RX_CHMUX_XI2S_67</a>, 
<a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea4f5885668f79e682e8ffa887330e99de">XI2S_RX_CHMUX_WAVEGEN</a>
<br/>
 }</td></tr>
<tr class="memdesc:gace941535376f24ef90b44f160f55b70e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef specifies the input sources of the the XI2s Receiver.  <a href="group__i2srx.html#gace941535376f24ef90b44f160f55b70e">More...</a><br/></td></tr>
<tr class="separator:gace941535376f24ef90b44f160f55b70e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga787bbfc7c06021fa68c40dd4e1248ec1"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga787bbfc7c06021fa68c40dd4e1248ec1">XI2s_Rx_Justification</a> { <a class="el" href="group__i2srx.html#gga787bbfc7c06021fa68c40dd4e1248ec1aa461181648e4f912e5f6bf33b922dae8">XI2S_RX_JUSTIFY_LEFT</a> = 0, 
<a class="el" href="group__i2srx.html#gga787bbfc7c06021fa68c40dd4e1248ec1a9bd0f58e092109daff42c8007ef31110">XI2S_RX_JUSTIFY_RIGHT</a>
 }</td></tr>
<tr class="memdesc:ga787bbfc7c06021fa68c40dd4e1248ec1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef specifies the justification of the the XI2s Receiver.  <a href="group__i2srx.html#ga787bbfc7c06021fa68c40dd4e1248ec1">More...</a><br/></td></tr>
<tr class="separator:ga787bbfc7c06021fa68c40dd4e1248ec1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga4d444eaa5a0dd7d980c0d216b3382260"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga4d444eaa5a0dd7d980c0d216b3382260">XI2s_Rx_CfgInitialize</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, <a class="el" href="struct_x_i2srx___config.html">XI2srx_Config</a> *CfgPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:ga4d444eaa5a0dd7d980c0d216b3382260"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes the XI2s Receiver.  <a href="#ga4d444eaa5a0dd7d980c0d216b3382260">More...</a><br/></td></tr>
<tr class="separator:ga4d444eaa5a0dd7d980c0d216b3382260"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a853463222fc023817337626e04ea1a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga3a853463222fc023817337626e04ea1a">XI2s_Rx_Enable</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, u8 Enable)</td></tr>
<tr class="memdesc:ga3a853463222fc023817337626e04ea1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables/disables the XI2s Receiver.  <a href="#ga3a853463222fc023817337626e04ea1a">More...</a><br/></td></tr>
<tr class="separator:ga3a853463222fc023817337626e04ea1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae745a449c173356fad2c4f4d3f19d9e0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gae745a449c173356fad2c4f4d3f19d9e0">XI2s_Rx_LatchAesChannelStatus</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr)</td></tr>
<tr class="memdesc:gae745a449c173356fad2c4f4d3f19d9e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function requests the XI2s Receiver to latch the AES Channel Status bits from the registers.  <a href="#gae745a449c173356fad2c4f4d3f19d9e0">More...</a><br/></td></tr>
<tr class="separator:gae745a449c173356fad2c4f4d3f19d9e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga595ca2872d1b5b59f05a229b3a28fd86"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga595ca2872d1b5b59f05a229b3a28fd86">XI2s_Rx_IntrEnable</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, u32 Mask)</td></tr>
<tr class="memdesc:ga595ca2872d1b5b59f05a229b3a28fd86"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the specified interrupt of the XI2s Receiver.  <a href="#ga595ca2872d1b5b59f05a229b3a28fd86">More...</a><br/></td></tr>
<tr class="separator:ga595ca2872d1b5b59f05a229b3a28fd86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80556a73ef85dd5a4731afab9ad10f22"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga80556a73ef85dd5a4731afab9ad10f22">XI2s_Rx_IntrDisable</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, u32 Mask)</td></tr>
<tr class="memdesc:ga80556a73ef85dd5a4731afab9ad10f22"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function disables the specified interrupt of the XI2s Receiver.  <a href="#ga80556a73ef85dd5a4731afab9ad10f22">More...</a><br/></td></tr>
<tr class="separator:ga80556a73ef85dd5a4731afab9ad10f22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga522d6260d91826f18572844fb0fbf39d"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga522d6260d91826f18572844fb0fbf39d">XI2s_Rx_SetChMux</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, <a class="el" href="group__i2srx.html#ga29fe382428db32ed7ad00cd1082609e2">XI2s_Rx_ChannelId</a> ChID, <a class="el" href="group__i2srx.html#gace941535376f24ef90b44f160f55b70e">XI2s_Rx_ChMuxInput</a> InputSource)</td></tr>
<tr class="memdesc:ga522d6260d91826f18572844fb0fbf39d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the input source for the specified AXI-Stream channel pair.  <a href="#ga522d6260d91826f18572844fb0fbf39d">More...</a><br/></td></tr>
<tr class="separator:ga522d6260d91826f18572844fb0fbf39d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b26d3fc18f6a8a65f2a55eb94300aac"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga6b26d3fc18f6a8a65f2a55eb94300aac">XI2s_Rx_SetSclkOutDiv</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, u32 MClk, u32 Fs)</td></tr>
<tr class="memdesc:ga6b26d3fc18f6a8a65f2a55eb94300aac"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the SCLK Output divider value of the I2s timing generator.  <a href="#ga6b26d3fc18f6a8a65f2a55eb94300aac">More...</a><br/></td></tr>
<tr class="separator:ga6b26d3fc18f6a8a65f2a55eb94300aac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0732ac9b13399678fe408cf55eeab264"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga0732ac9b13399678fe408cf55eeab264">XI2s_Rx_SetAesChStatus</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, u8 *AesChStatusBuf)</td></tr>
<tr class="memdesc:ga0732ac9b13399678fe408cf55eeab264"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the AES Channel Status bits to insert.  <a href="#ga0732ac9b13399678fe408cf55eeab264">More...</a><br/></td></tr>
<tr class="separator:ga0732ac9b13399678fe408cf55eeab264"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga700662592a50d2f7ee92aff8304706f3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga700662592a50d2f7ee92aff8304706f3">XI2s_Rx_ClrAesChStatRegs</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga700662592a50d2f7ee92aff8304706f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the captured AES Channel Status bits.  <a href="#ga700662592a50d2f7ee92aff8304706f3">More...</a><br/></td></tr>
<tr class="separator:ga700662592a50d2f7ee92aff8304706f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4407276f62220e4983d6ec7251ad98d6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga4407276f62220e4983d6ec7251ad98d6">XI2s_Rx_JustifyEnable</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, u8 Enable)</td></tr>
<tr class="memdesc:ga4407276f62220e4983d6ec7251ad98d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables/disables the justification.  <a href="#ga4407276f62220e4983d6ec7251ad98d6">More...</a><br/></td></tr>
<tr class="separator:ga4407276f62220e4983d6ec7251ad98d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68a5ca9532a69737b7d8788edd9f822d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga68a5ca9532a69737b7d8788edd9f822d">XI2s_Rx_Justify</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, <a class="el" href="group__i2srx.html#ga787bbfc7c06021fa68c40dd4e1248ec1">XI2s_Rx_Justification</a> Justify)</td></tr>
<tr class="memdesc:ga68a5ca9532a69737b7d8788edd9f822d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is to enable right/left justification.  <a href="#ga68a5ca9532a69737b7d8788edd9f822d">More...</a><br/></td></tr>
<tr class="separator:ga68a5ca9532a69737b7d8788edd9f822d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8be6ac54842b054fb0f5b047669a794c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga8be6ac54842b054fb0f5b047669a794c">XI2s_Rx_SelfTest</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga8be6ac54842b054fb0f5b047669a794c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a self-test on the driver/device.  <a href="#ga8be6ac54842b054fb0f5b047669a794c">More...</a><br/></td></tr>
<tr class="separator:ga8be6ac54842b054fb0f5b047669a794c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga86fad2b52bbb42c12f21c72463a614b5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_i2srx___config.html">XI2srx_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga86fad2b52bbb42c12f21c72463a614b5">XI2s_Rx_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:ga86fad2b52bbb42c12f21c72463a614b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns a reference to an <a class="el" href="struct_x_i2srx___config.html" title="This typedef contains configuration information for the XI2s Receiver. ">XI2srx_Config</a> structure based on the core id, <em>DeviceId</em>.  <a href="#ga86fad2b52bbb42c12f21c72463a614b5">More...</a><br/></td></tr>
<tr class="separator:ga86fad2b52bbb42c12f21c72463a614b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga164f49a595611f6092889fbc157982f4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga164f49a595611f6092889fbc157982f4">XI2s_Rx_Initialize</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, u16 DeviceId)</td></tr>
<tr class="memdesc:ga164f49a595611f6092889fbc157982f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes a specific <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance such that the driver is ready to use.  <a href="#ga164f49a595611f6092889fbc157982f4">More...</a><br/></td></tr>
<tr class="separator:ga164f49a595611f6092889fbc157982f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca17a3387ef6bb0acdcfd20b94c0b7b1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaca17a3387ef6bb0acdcfd20b94c0b7b1">XI2s_Rx_IntrHandler</a> (void *InstancePtr)</td></tr>
<tr class="memdesc:gaca17a3387ef6bb0acdcfd20b94c0b7b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the interrupt handler for the XI2s Receiver driver.  <a href="#gaca17a3387ef6bb0acdcfd20b94c0b7b1">More...</a><br/></td></tr>
<tr class="separator:gaca17a3387ef6bb0acdcfd20b94c0b7b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac365d1ba8ad9aca6ed6ebde4be5da1be"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gac365d1ba8ad9aca6ed6ebde4be5da1be">XI2s_Rx_SetHandler</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, <a class="el" href="group__i2srx.html#ga73cea697b9b2b7edb411ac4ecf01b349">XI2s_Rx_HandlerType</a> HandlerType, <a class="el" href="group__i2srx.html#gaef13cc9c4d09dc05e1027c43bc2aeed2">XI2s_Rx_Callback</a> FuncPtr, void *CallbackRef)</td></tr>
<tr class="memdesc:gac365d1ba8ad9aca6ed6ebde4be5da1be"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs an asynchronous callback function for the given HandlerType:  <a href="#gac365d1ba8ad9aca6ed6ebde4be5da1be">More...</a><br/></td></tr>
<tr class="separator:gac365d1ba8ad9aca6ed6ebde4be5da1be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad30090fdf63b203192a837ca5860992b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gad30090fdf63b203192a837ca5860992b">XI2s_Rx_LogDisplay</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr)</td></tr>
<tr class="memdesc:gad30090fdf63b203192a837ca5860992b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints the contents of the logging buffer.  <a href="#gad30090fdf63b203192a837ca5860992b">More...</a><br/></td></tr>
<tr class="separator:gad30090fdf63b203192a837ca5860992b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8525e3230b25c045bd85afa33346e624"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga8525e3230b25c045bd85afa33346e624">XI2s_Rx_LogReset</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga8525e3230b25c045bd85afa33346e624"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the contents of the logging buffer.  <a href="#ga8525e3230b25c045bd85afa33346e624">More...</a><br/></td></tr>
<tr class="separator:ga8525e3230b25c045bd85afa33346e624"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad797c77106bcc4da0a72e65e5620fa02"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gad797c77106bcc4da0a72e65e5620fa02">XI2s_Rx_LogWrite</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr, <a class="el" href="group__i2srx.html#ga4fecc6c86b725108f3488292d518816c">XI2s_Rx_LogEvt</a> Event, u8 Data)</td></tr>
<tr class="memdesc:gad797c77106bcc4da0a72e65e5620fa02"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes XI2s Receiver logs into the buffer.  <a href="#gad797c77106bcc4da0a72e65e5620fa02">More...</a><br/></td></tr>
<tr class="separator:gad797c77106bcc4da0a72e65e5620fa02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace02e57eaf489fffb38e0f3d4f69c8d3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_i2s___rx___log_item.html">XI2s_Rx_LogItem</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gace02e57eaf489fffb38e0f3d4f69c8d3">XI2s_Rx_LogRead</a> (<a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *InstancePtr)</td></tr>
<tr class="memdesc:gace02e57eaf489fffb38e0f3d4f69c8d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the next item in the logging buffer.  <a href="#gace02e57eaf489fffb38e0f3d4f69c8d3">More...</a><br/></td></tr>
<tr class="separator:gace02e57eaf489fffb38e0f3d4f69c8d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga43cf5550c0ab230211f2fec6a77f46d5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga43cf5550c0ab230211f2fec6a77f46d5">XI2s_Rx_SetAesChStat</a> (u32 I2srx_SrcBuf[], u8 I2srx_DstBuf[])</td></tr>
<tr class="memdesc:ga43cf5550c0ab230211f2fec6a77f46d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the source buffer and writes to a destination buffer.  <a href="#ga43cf5550c0ab230211f2fec6a77f46d5">More...</a><br/></td></tr>
<tr class="separator:ga43cf5550c0ab230211f2fec6a77f46d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Handler Types</h2></td></tr>
<tr class="memitem:ga73cea697b9b2b7edb411ac4ecf01b349"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga73cea697b9b2b7edb411ac4ecf01b349">XI2s_Rx_HandlerType</a> { <a class="el" href="group__i2srx.html#gga73cea697b9b2b7edb411ac4ecf01b349ad5a32351d829855baf3f691a3718d176">XI2S_RX_HANDLER_AES_BLKCMPLT</a> = 0, 
<a class="el" href="group__i2srx.html#gga73cea697b9b2b7edb411ac4ecf01b349adbc31f3ef63cffa075c18ad2a1288b0d">XI2S_RX_HANDLER_AUD_OVRFLW</a>, 
<a class="el" href="group__i2srx.html#gga73cea697b9b2b7edb411ac4ecf01b349a743f017dc379e345fa2511aa81fc3621">XI2S_RX_NUM_HANDLERS</a>
 }</td></tr>
<tr class="memdesc:ga73cea697b9b2b7edb411ac4ecf01b349"><td class="mdescLeft">&#160;</td><td class="mdescRight">These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral.  <a href="group__i2srx.html#ga73cea697b9b2b7edb411ac4ecf01b349">More...</a><br/></td></tr>
<tr class="separator:ga73cea697b9b2b7edb411ac4ecf01b349"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29fe382428db32ed7ad00cd1082609e2"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga29fe382428db32ed7ad00cd1082609e2">XI2s_Rx_ChannelId</a> { <br/>
&#160;&#160;<a class="el" href="group__i2srx.html#gga29fe382428db32ed7ad00cd1082609e2a0d5df5d0173cff1b2ddfda530698d4d6">XI2S_RX_CHID0</a> = 0, 
<a class="el" href="group__i2srx.html#gga29fe382428db32ed7ad00cd1082609e2aa4e1404437e2db8108a9b6da4ba5fd03">XI2S_RX_CHID1</a>, 
<a class="el" href="group__i2srx.html#gga29fe382428db32ed7ad00cd1082609e2ae0fcdcc15c32a53bd6b7e907cbc89e6a">XI2S_RX_CHID2</a>, 
<a class="el" href="group__i2srx.html#gga29fe382428db32ed7ad00cd1082609e2aec3f40e4bcd10c6af7fbbf987a89e4db">XI2S_RX_CHID3</a>, 
<br/>
&#160;&#160;<a class="el" href="group__i2srx.html#gga29fe382428db32ed7ad00cd1082609e2a3c8607ad2a5133fa10d64bbcf6c37e20">XI2S_RX_NUM_CHANNELS</a>
<br/>
 }</td></tr>
<tr class="memdesc:ga29fe382428db32ed7ad00cd1082609e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">These constants specify different channel ID's.  <a href="group__i2srx.html#ga29fe382428db32ed7ad00cd1082609e2">More...</a><br/></td></tr>
<tr class="separator:ga29fe382428db32ed7ad00cd1082609e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf209d23e3a0830d768f89eae49aa1be2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaf209d23e3a0830d768f89eae49aa1be2">XI2S_RX_LOG_ITEM_BUFFER_SIZE</a>&#160;&#160;&#160;(256)</td></tr>
<tr class="memdesc:gaf209d23e3a0830d768f89eae49aa1be2"><td class="mdescLeft">&#160;</td><td class="mdescRight">@ name Log Item Buffer Size  <a href="#gaf209d23e3a0830d768f89eae49aa1be2">More...</a><br/></td></tr>
<tr class="separator:gaf209d23e3a0830d768f89eae49aa1be2"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Handler Types</h2></td></tr>
<tr class="memitem:ga4fecc6c86b725108f3488292d518816c"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga4fecc6c86b725108f3488292d518816c">XI2s_Rx_LogEvt</a> { <a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816cafcbc177f865f01745336004358d4479e">XI2S_RX_AES_BLKCMPLT_EVT</a>, 
<a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816caac11c46eda786e90c37a6bc1dac96897">XI2S_RX_AUD_OVERFLOW_EVT</a>, 
<a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816cabd013a083c7841b935a6f5f5d38d45a5">XI2S_RX_LOG_EVT_INVALID</a>
 }</td></tr>
<tr class="memdesc:ga4fecc6c86b725108f3488292d518816c"><td class="mdescLeft">&#160;</td><td class="mdescRight">These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral.  <a href="group__i2srx.html#ga4fecc6c86b725108f3488292d518816c">More...</a><br/></td></tr>
<tr class="separator:ga4fecc6c86b725108f3488292d518816c"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Register Map</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp092729737d14686054aa21531a3582c6"></a>Register offsets for the XI2srx device. </p>
</td></tr>
<tr class="memitem:gabd6a5cdc267deb874be64ecff6b93e4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gabd6a5cdc267deb874be64ecff6b93e4b">XI2S_RX_CORE_VER_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gabd6a5cdc267deb874be64ecff6b93e4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Version Register.  <a href="#gabd6a5cdc267deb874be64ecff6b93e4b">More...</a><br/></td></tr>
<tr class="separator:gabd6a5cdc267deb874be64ecff6b93e4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab2f8c799ff6de247d102de9eca1578c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaab2f8c799ff6de247d102de9eca1578c">XI2S_RX_CORE_CFG_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:gaab2f8c799ff6de247d102de9eca1578c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Configuration Register.  <a href="#gaab2f8c799ff6de247d102de9eca1578c">More...</a><br/></td></tr>
<tr class="separator:gaab2f8c799ff6de247d102de9eca1578c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa79a92debd04aa3b8f9866869fcee2ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaa79a92debd04aa3b8f9866869fcee2ea">XI2S_RX_CORE_CTRL_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:gaa79a92debd04aa3b8f9866869fcee2ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Control Register.  <a href="#gaa79a92debd04aa3b8f9866869fcee2ea">More...</a><br/></td></tr>
<tr class="separator:gaa79a92debd04aa3b8f9866869fcee2ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d9730105131e980b1b2ca3996969f31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga9d9730105131e980b1b2ca3996969f31">XI2S_RX_IRQCTRL_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:ga9d9730105131e980b1b2ca3996969f31"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Control Register.  <a href="#ga9d9730105131e980b1b2ca3996969f31">More...</a><br/></td></tr>
<tr class="separator:ga9d9730105131e980b1b2ca3996969f31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10ebd12832c0df2b25d86e1c426917a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga10ebd12832c0df2b25d86e1c426917a2">XI2S_RX_IRQSTS_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ga10ebd12832c0df2b25d86e1c426917a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="#ga10ebd12832c0df2b25d86e1c426917a2">More...</a><br/></td></tr>
<tr class="separator:ga10ebd12832c0df2b25d86e1c426917a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad10e1d11d2c50b2111dd3f8a4dd26389"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gad10e1d11d2c50b2111dd3f8a4dd26389">XI2S_RX_TMR_CTRL_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:gad10e1d11d2c50b2111dd3f8a4dd26389"><td class="mdescLeft">&#160;</td><td class="mdescRight">XI2S Timing Control Register.  <a href="#gad10e1d11d2c50b2111dd3f8a4dd26389">More...</a><br/></td></tr>
<tr class="separator:gad10e1d11d2c50b2111dd3f8a4dd26389"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc668d400426098bae3149a9fc4c094f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gacc668d400426098bae3149a9fc4c094f">XI2S_RX_CH01_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:gacc668d400426098bae3149a9fc4c094f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 0/1 Control Register.  <a href="#gacc668d400426098bae3149a9fc4c094f">More...</a><br/></td></tr>
<tr class="separator:gacc668d400426098bae3149a9fc4c094f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d7fe447197f14d38b515caa072893b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga7d7fe447197f14d38b515caa072893b7">XI2S_RX_CH23_OFFSET</a>&#160;&#160;&#160;0x34</td></tr>
<tr class="memdesc:ga7d7fe447197f14d38b515caa072893b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 2/3 Control Register.  <a href="#ga7d7fe447197f14d38b515caa072893b7">More...</a><br/></td></tr>
<tr class="separator:ga7d7fe447197f14d38b515caa072893b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29d0c7f997d393d644e6374ea70e6ac2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga29d0c7f997d393d644e6374ea70e6ac2">XI2S_RX_CH45_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:ga29d0c7f997d393d644e6374ea70e6ac2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 4/5 Control Register.  <a href="#ga29d0c7f997d393d644e6374ea70e6ac2">More...</a><br/></td></tr>
<tr class="separator:ga29d0c7f997d393d644e6374ea70e6ac2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae40a3a7ebb7cee1e4a3d935e6b51569f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gae40a3a7ebb7cee1e4a3d935e6b51569f">XI2S_RX_CH67_OFFSET</a>&#160;&#160;&#160;0x3C</td></tr>
<tr class="memdesc:gae40a3a7ebb7cee1e4a3d935e6b51569f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 6/7 Control Register.  <a href="#gae40a3a7ebb7cee1e4a3d935e6b51569f">More...</a><br/></td></tr>
<tr class="separator:gae40a3a7ebb7cee1e4a3d935e6b51569f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef854c082d18fb31d75d15c23aa7fab5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaef854c082d18fb31d75d15c23aa7fab5">XI2S_RX_AES_CHSTS0_OFFSET</a>&#160;&#160;&#160;0x50</td></tr>
<tr class="memdesc:gaef854c082d18fb31d75d15c23aa7fab5"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 0 Register.  <a href="#gaef854c082d18fb31d75d15c23aa7fab5">More...</a><br/></td></tr>
<tr class="separator:gaef854c082d18fb31d75d15c23aa7fab5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6eb6685030ce7a4097e2d26591026109"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga6eb6685030ce7a4097e2d26591026109">XI2S_RX_AES_CHSTS1_OFFSET</a>&#160;&#160;&#160;0x54</td></tr>
<tr class="memdesc:ga6eb6685030ce7a4097e2d26591026109"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 1 Register.  <a href="#ga6eb6685030ce7a4097e2d26591026109">More...</a><br/></td></tr>
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<tr class="memitem:ga4a5e64ec439b371f7dbb7795796ea525"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga4a5e64ec439b371f7dbb7795796ea525">XI2S_RX_AES_CHSTS2_OFFSET</a>&#160;&#160;&#160;0x58</td></tr>
<tr class="memdesc:ga4a5e64ec439b371f7dbb7795796ea525"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 2 Register.  <a href="#ga4a5e64ec439b371f7dbb7795796ea525">More...</a><br/></td></tr>
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<tr class="memitem:ga5aec8ad439da8047b7e2406680091bb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga5aec8ad439da8047b7e2406680091bb3">XI2S_RX_AES_CHSTS3_OFFSET</a>&#160;&#160;&#160;0x5C</td></tr>
<tr class="memdesc:ga5aec8ad439da8047b7e2406680091bb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 3 Register.  <a href="#ga5aec8ad439da8047b7e2406680091bb3">More...</a><br/></td></tr>
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<tr class="memitem:ga64228e861649cfca19122186738890c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga64228e861649cfca19122186738890c3">XI2S_RX_AES_CHSTS4_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:ga64228e861649cfca19122186738890c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 4 Register.  <a href="#ga64228e861649cfca19122186738890c3">More...</a><br/></td></tr>
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<tr class="memitem:gada5ad0f01fc6b245bc58fb0ac66f3672"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gada5ad0f01fc6b245bc58fb0ac66f3672">XI2S_RX_AES_CHSTS5_OFFSET</a>&#160;&#160;&#160;0x64</td></tr>
<tr class="memdesc:gada5ad0f01fc6b245bc58fb0ac66f3672"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 5 Register.  <a href="#gada5ad0f01fc6b245bc58fb0ac66f3672">More...</a><br/></td></tr>
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Core Configuration Register masks and shifts</h2></td></tr>
<tr class="memitem:ga386baab9d9d9e77e9569f78f8535c79a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga386baab9d9d9e77e9569f78f8535c79a">XI2S_RX_REG_CFG_MSTR_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga386baab9d9d9e77e9569f78f8535c79a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XI2S Master bit shift.  <a href="#ga386baab9d9d9e77e9569f78f8535c79a">More...</a><br/></td></tr>
<tr class="separator:ga386baab9d9d9e77e9569f78f8535c79a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc9bad93a6ce59caa98a961eca5180fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gacc9bad93a6ce59caa98a961eca5180fd">XI2S_RX_REG_CFG_MSTR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga386baab9d9d9e77e9569f78f8535c79a">XI2S_RX_REG_CFG_MSTR_SHIFT</a>)</td></tr>
<tr class="memdesc:gacc9bad93a6ce59caa98a961eca5180fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XI2S Master mask.  <a href="#gacc9bad93a6ce59caa98a961eca5180fd">More...</a><br/></td></tr>
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<tr class="memitem:ga33b447ccf86e1d8e207cd5b04cc0e0bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga33b447ccf86e1d8e207cd5b04cc0e0bd">XI2S_RX_REG_CFG_NUM_CH_SHIFT</a>&#160;&#160;&#160;(8)</td></tr>
<tr class="memdesc:ga33b447ccf86e1d8e207cd5b04cc0e0bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of channels bit shift.  <a href="#ga33b447ccf86e1d8e207cd5b04cc0e0bd">More...</a><br/></td></tr>
<tr class="separator:ga33b447ccf86e1d8e207cd5b04cc0e0bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f0aaac08ca351e2389bbe04a8b6a87f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga6f0aaac08ca351e2389bbe04a8b6a87f">XI2S_RX_REG_CFG_NUM_CH_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_RX_REG_CFG_NUM_CH_SHIFT)</td></tr>
<tr class="memdesc:ga6f0aaac08ca351e2389bbe04a8b6a87f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of channels mask.  <a href="#ga6f0aaac08ca351e2389bbe04a8b6a87f">More...</a><br/></td></tr>
<tr class="separator:ga6f0aaac08ca351e2389bbe04a8b6a87f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9cf777ebbfe32e3744fc3ec6e7b0b439"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga9cf777ebbfe32e3744fc3ec6e7b0b439">XI2S_RX_REG_CFG_DWDTH_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:ga9cf777ebbfe32e3744fc3ec6e7b0b439"><td class="mdescLeft">&#160;</td><td class="mdescRight">XI2S Data Width bit shift.  <a href="#ga9cf777ebbfe32e3744fc3ec6e7b0b439">More...</a><br/></td></tr>
<tr class="separator:ga9cf777ebbfe32e3744fc3ec6e7b0b439"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e6c0504d9ddf7ecb2301b76815d7fc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga8e6c0504d9ddf7ecb2301b76815d7fc4">XI2S_RX_REG_CFG_DWDTH_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga9cf777ebbfe32e3744fc3ec6e7b0b439">XI2S_RX_REG_CFG_DWDTH_SHIFT</a>)</td></tr>
<tr class="memdesc:ga8e6c0504d9ddf7ecb2301b76815d7fc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">XI2S Data Width mask.  <a href="#ga8e6c0504d9ddf7ecb2301b76815d7fc4">More...</a><br/></td></tr>
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Core Control Register masks and shifts</h2></td></tr>
<tr class="memitem:ga2b6fec3d30ffb6d6e75686cbd6050d05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga2b6fec3d30ffb6d6e75686cbd6050d05">XI2S_RX_REG_CTRL_EN_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga2b6fec3d30ffb6d6e75686cbd6050d05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module Enable bit shift.  <a href="#ga2b6fec3d30ffb6d6e75686cbd6050d05">More...</a><br/></td></tr>
<tr class="separator:ga2b6fec3d30ffb6d6e75686cbd6050d05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72d3a8ea524c40940140512a982fb910"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga72d3a8ea524c40940140512a982fb910">XI2S_RX_REG_CTRL_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga2b6fec3d30ffb6d6e75686cbd6050d05">XI2S_RX_REG_CTRL_EN_SHIFT</a>)</td></tr>
<tr class="memdesc:ga72d3a8ea524c40940140512a982fb910"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module Enable mask.  <a href="#ga72d3a8ea524c40940140512a982fb910">More...</a><br/></td></tr>
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<tr class="memitem:gac9e9f8391850f0ca4407e7fda7b3c7d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gac9e9f8391850f0ca4407e7fda7b3c7d6">XI2S_RX_REG_CTRL_JFE_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:gac9e9f8391850f0ca4407e7fda7b3c7d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Justification Enable or Disable shift.  <a href="#gac9e9f8391850f0ca4407e7fda7b3c7d6">More...</a><br/></td></tr>
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<tr class="memitem:ga4bed9d26f96c101a80fdeb5e16c61882"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga4bed9d26f96c101a80fdeb5e16c61882">XI2S_RX_REG_CTRL_JFE_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gac9e9f8391850f0ca4407e7fda7b3c7d6">XI2S_RX_REG_CTRL_JFE_SHIFT</a>)</td></tr>
<tr class="memdesc:ga4bed9d26f96c101a80fdeb5e16c61882"><td class="mdescLeft">&#160;</td><td class="mdescRight">Justification Enable or Disable mask.  <a href="#ga4bed9d26f96c101a80fdeb5e16c61882">More...</a><br/></td></tr>
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<tr class="memitem:gaf733f45be6a7f7c489c2ef5a0faf1cc1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaf733f45be6a7f7c489c2ef5a0faf1cc1">XI2S_RX_REG_CTRL_LORJF_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:gaf733f45be6a7f7c489c2ef5a0faf1cc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Left or Right Justification shift.  <a href="#gaf733f45be6a7f7c489c2ef5a0faf1cc1">More...</a><br/></td></tr>
<tr class="separator:gaf733f45be6a7f7c489c2ef5a0faf1cc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1e05f03cc894aaa4e5bf213460eeb43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gae1e05f03cc894aaa4e5bf213460eeb43">XI2S_RX_REG_CTRL_LORJF_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gaf733f45be6a7f7c489c2ef5a0faf1cc1">XI2S_RX_REG_CTRL_LORJF_SHIFT</a>)</td></tr>
<tr class="memdesc:gae1e05f03cc894aaa4e5bf213460eeb43"><td class="mdescLeft">&#160;</td><td class="mdescRight">Left or Right Justification mask.  <a href="#gae1e05f03cc894aaa4e5bf213460eeb43">More...</a><br/></td></tr>
<tr class="separator:gae1e05f03cc894aaa4e5bf213460eeb43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a4b4b0ed331511eea0872abe6d1a008"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga2a4b4b0ed331511eea0872abe6d1a008">XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:ga2a4b4b0ed331511eea0872abe6d1a008"><td class="mdescLeft">&#160;</td><td class="mdescRight">Latch AES Channel Status bit shift.  <a href="#ga2a4b4b0ed331511eea0872abe6d1a008">More...</a><br/></td></tr>
<tr class="separator:ga2a4b4b0ed331511eea0872abe6d1a008"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1cb52ffff197179ecb2453f3b055f2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gab1cb52ffff197179ecb2453f3b055f2e">XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga2a4b4b0ed331511eea0872abe6d1a008">XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT</a>)</td></tr>
<tr class="memdesc:gab1cb52ffff197179ecb2453f3b055f2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Latch AES Channel Status mask.  <a href="#gab1cb52ffff197179ecb2453f3b055f2e">More...</a><br/></td></tr>
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Interrupt masks and shifts</h2></td></tr>
<tr class="memitem:gaeeff2f78e8d4799f14b13f5dd74f07ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaeeff2f78e8d4799f14b13f5dd74f07ac">XI2S_RX_INTR_AES_BLKCMPLT_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gaeeff2f78e8d4799f14b13f5dd74f07ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Complete Interrupt bit shift.  <a href="#gaeeff2f78e8d4799f14b13f5dd74f07ac">More...</a><br/></td></tr>
<tr class="separator:gaeeff2f78e8d4799f14b13f5dd74f07ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa37ac42887b7ca3d17a5a48af43c3d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gafa37ac42887b7ca3d17a5a48af43c3d1">XI2S_RX_INTR_AES_BLKCMPLT_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gaeeff2f78e8d4799f14b13f5dd74f07ac">XI2S_RX_INTR_AES_BLKCMPLT_SHIFT</a>)</td></tr>
<tr class="memdesc:gafa37ac42887b7ca3d17a5a48af43c3d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Complete Interrupt mask.  <a href="#gafa37ac42887b7ca3d17a5a48af43c3d1">More...</a><br/></td></tr>
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<tr class="memitem:ga12970ee31e47fcfe72564f65923519ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga12970ee31e47fcfe72564f65923519ff">XI2S_RX_INTR_AUDOVRFLW_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:ga12970ee31e47fcfe72564f65923519ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Overflow Detected Interrupt bit shift.  <a href="#ga12970ee31e47fcfe72564f65923519ff">More...</a><br/></td></tr>
<tr class="separator:ga12970ee31e47fcfe72564f65923519ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf7d542116f93c176f729165c0c0ab46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gacf7d542116f93c176f729165c0c0ab46">XI2S_RX_INTR_AUDOVRFLW_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga12970ee31e47fcfe72564f65923519ff">XI2S_RX_INTR_AUDOVRFLW_SHIFT</a>)</td></tr>
<tr class="memdesc:gacf7d542116f93c176f729165c0c0ab46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Overflow Detected Interrupt mask.  <a href="#gacf7d542116f93c176f729165c0c0ab46">More...</a><br/></td></tr>
<tr class="separator:gacf7d542116f93c176f729165c0c0ab46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ff2b2e7bc857175d47e3b396337c3c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga6ff2b2e7bc857175d47e3b396337c3c8">XI2S_RX_GINTR_EN_SHIFT</a>&#160;&#160;&#160;(31)</td></tr>
<tr class="memdesc:ga6ff2b2e7bc857175d47e3b396337c3c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable bit shift.  <a href="#ga6ff2b2e7bc857175d47e3b396337c3c8">More...</a><br/></td></tr>
<tr class="separator:ga6ff2b2e7bc857175d47e3b396337c3c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7089f6d78ab940b47ac4e63cc9de876d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga7089f6d78ab940b47ac4e63cc9de876d">XI2S_RX_GINTR_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga6ff2b2e7bc857175d47e3b396337c3c8">XI2S_RX_GINTR_EN_SHIFT</a>)</td></tr>
<tr class="memdesc:ga7089f6d78ab940b47ac4e63cc9de876d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable mask.  <a href="#ga7089f6d78ab940b47ac4e63cc9de876d">More...</a><br/></td></tr>
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XI2S Timing Control Register masks and shifts</h2></td></tr>
<tr class="memitem:gab3b615049121f07d4a919c3a36866598"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gab3b615049121f07d4a919c3a36866598">XI2S_RX_REG_TMR_SCLKDIV_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gab3b615049121f07d4a919c3a36866598"><td class="mdescLeft">&#160;</td><td class="mdescRight">SClk Divider bit shift.  <a href="#gab3b615049121f07d4a919c3a36866598">More...</a><br/></td></tr>
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<tr class="memitem:ga0a6e25d96079222ab136c05ab1040bf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga0a6e25d96079222ab136c05ab1040bf6">XI2S_RX_REG_TMR_SCLKDIV_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_RX_REG_TMR_SCLKDIV_SHIFT)</td></tr>
<tr class="memdesc:ga0a6e25d96079222ab136c05ab1040bf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SClk Divider mask.  <a href="#ga0a6e25d96079222ab136c05ab1040bf6">More...</a><br/></td></tr>
<tr class="separator:ga0a6e25d96079222ab136c05ab1040bf6"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Audio Channel Control Register masks and shifts</h2></td></tr>
<tr class="memitem:gac24b161236882834c75e99865405aed4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gac24b161236882834c75e99865405aed4">XI2S_RX_REG_CHCTRL_CHMUX_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gac24b161236882834c75e99865405aed4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel MUX bit shift.  <a href="#gac24b161236882834c75e99865405aed4">More...</a><br/></td></tr>
<tr class="separator:gac24b161236882834c75e99865405aed4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55cd99e10d5e57674583e973d07cd1f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga55cd99e10d5e57674583e973d07cd1f3">XI2S_RX_REG_CHCTRL_CHMUX_MASK</a>&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_RX_REG_CHCTRL_CHMUX_SHIFT)</td></tr>
<tr class="memdesc:ga55cd99e10d5e57674583e973d07cd1f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel MUX mask.  <a href="#ga55cd99e10d5e57674583e973d07cd1f3">More...</a><br/></td></tr>
<tr class="separator:ga55cd99e10d5e57674583e973d07cd1f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Register access macro definition</h2></td></tr>
<tr class="memitem:ga09a5bac7db972eedb59f8a333b9ab962"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga09a5bac7db972eedb59f8a333b9ab962">XI2s_Rx_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:ga09a5bac7db972eedb59f8a333b9ab962"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#ga09a5bac7db972eedb59f8a333b9ab962">More...</a><br/></td></tr>
<tr class="separator:ga09a5bac7db972eedb59f8a333b9ab962"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadab8698c5b4c02161f42cfc947c5d1b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gadab8698c5b4c02161f42cfc947c5d1b2">XI2s_Rx_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:gadab8698c5b4c02161f42cfc947c5d1b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#gadab8698c5b4c02161f42cfc947c5d1b2">More...</a><br/></td></tr>
<tr class="separator:gadab8698c5b4c02161f42cfc947c5d1b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f13e37d826cfd786b54f7ad04c0fd3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="group__i2srx.html#ga09a5bac7db972eedb59f8a333b9ab962">XI2s_Rx_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="memdesc:ga7f13e37d826cfd786b54f7ad04c0fd3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a XI2s Receiver register.  <a href="#ga7f13e37d826cfd786b54f7ad04c0fd3c">More...</a><br/></td></tr>
<tr class="separator:ga7f13e37d826cfd786b54f7ad04c0fd3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac98a6dde12e4efc76872f80b47fe641f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="group__i2srx.html#gadab8698c5b4c02161f42cfc947c5d1b2">XI2s_Rx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:gac98a6dde12e4efc76872f80b47fe641f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a XI2s Receiver register.  <a href="#gac98a6dde12e4efc76872f80b47fe641f">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="gaef854c082d18fb31d75d15c23aa7fab5"></a>
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          <td class="memname">#define XI2S_RX_AES_CHSTS0_OFFSET&#160;&#160;&#160;0x50</td>
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<p>AES Channel Status 0 Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga700662592a50d2f7ee92aff8304706f3">XI2s_Rx_ClrAesChStatRegs()</a>, and <a class="el" href="group__i2srx.html#ga0732ac9b13399678fe408cf55eeab264">XI2s_Rx_SetAesChStatus()</a>.</p>

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</div>
<a class="anchor" id="ga6eb6685030ce7a4097e2d26591026109"></a>
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          <td class="memname">#define XI2S_RX_AES_CHSTS1_OFFSET&#160;&#160;&#160;0x54</td>
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<p>AES Channel Status 1 Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga700662592a50d2f7ee92aff8304706f3">XI2s_Rx_ClrAesChStatRegs()</a>.</p>

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<a class="anchor" id="ga4a5e64ec439b371f7dbb7795796ea525"></a>
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          <td class="memname">#define XI2S_RX_AES_CHSTS2_OFFSET&#160;&#160;&#160;0x58</td>
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<p>AES Channel Status 2 Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga700662592a50d2f7ee92aff8304706f3">XI2s_Rx_ClrAesChStatRegs()</a>.</p>

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</div>
<a class="anchor" id="ga5aec8ad439da8047b7e2406680091bb3"></a>
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          <td class="memname">#define XI2S_RX_AES_CHSTS3_OFFSET&#160;&#160;&#160;0x5C</td>
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<p>AES Channel Status 3 Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga700662592a50d2f7ee92aff8304706f3">XI2s_Rx_ClrAesChStatRegs()</a>.</p>

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<a class="anchor" id="ga64228e861649cfca19122186738890c3"></a>
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          <td class="memname">#define XI2S_RX_AES_CHSTS4_OFFSET&#160;&#160;&#160;0x60</td>
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<p>AES Channel Status 4 Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga700662592a50d2f7ee92aff8304706f3">XI2s_Rx_ClrAesChStatRegs()</a>.</p>

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<a class="anchor" id="gada5ad0f01fc6b245bc58fb0ac66f3672"></a>
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          <td class="memname">#define XI2S_RX_AES_CHSTS5_OFFSET&#160;&#160;&#160;0x64</td>
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<p>AES Channel Status 5 Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga700662592a50d2f7ee92aff8304706f3">XI2s_Rx_ClrAesChStatRegs()</a>.</p>

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<a class="anchor" id="gacc668d400426098bae3149a9fc4c094f"></a>
<div class="memitem">
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          <td class="memname">#define XI2S_RX_CH01_OFFSET&#160;&#160;&#160;0x30</td>
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<p>Audio Channel 0/1 Control Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga522d6260d91826f18572844fb0fbf39d">XI2s_Rx_SetChMux()</a>.</p>

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<a class="anchor" id="ga7d7fe447197f14d38b515caa072893b7"></a>
<div class="memitem">
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          <td class="memname">#define XI2S_RX_CH23_OFFSET&#160;&#160;&#160;0x34</td>
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<p>Audio Channel 2/3 Control Register. </p>

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<a class="anchor" id="ga29d0c7f997d393d644e6374ea70e6ac2"></a>
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          <td class="memname">#define XI2S_RX_CH45_OFFSET&#160;&#160;&#160;0x38</td>
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<p>Audio Channel 4/5 Control Register. </p>

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<a class="anchor" id="gae40a3a7ebb7cee1e4a3d935e6b51569f"></a>
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          <td class="memname">#define XI2S_RX_CH67_OFFSET&#160;&#160;&#160;0x3C</td>
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<p>Audio Channel 6/7 Control Register. </p>

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<a class="anchor" id="gaab2f8c799ff6de247d102de9eca1578c"></a>
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          <td class="memname">#define XI2S_RX_CORE_CFG_OFFSET&#160;&#160;&#160;0x04</td>
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<p>Core Configuration Register. </p>

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<a class="anchor" id="gaa79a92debd04aa3b8f9866869fcee2ea"></a>
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          <td class="memname">#define XI2S_RX_CORE_CTRL_OFFSET&#160;&#160;&#160;0x08</td>
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<p>Core Control Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga3a853463222fc023817337626e04ea1a">XI2s_Rx_Enable()</a>, <a class="el" href="group__i2srx.html#ga68a5ca9532a69737b7d8788edd9f822d">XI2s_Rx_Justify()</a>, <a class="el" href="group__i2srx.html#ga4407276f62220e4983d6ec7251ad98d6">XI2s_Rx_JustifyEnable()</a>, and <a class="el" href="group__i2srx.html#gae745a449c173356fad2c4f4d3f19d9e0">XI2s_Rx_LatchAesChannelStatus()</a>.</p>

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<a class="anchor" id="gabd6a5cdc267deb874be64ecff6b93e4b"></a>
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          <td class="memname">#define XI2S_RX_CORE_VER_OFFSET&#160;&#160;&#160;0x00</td>
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<p>Core Version Register. </p>

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<a class="anchor" id="ga7b7e72e5a3a6b2d4cbddf5f41545c574"></a>
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          <td class="memname">#define XI2s_Rx_GetMaxChannels</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
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<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, (<a class="code" href="group__i2srx.html#gaab2f8c799ff6de247d102de9eca1578c">XI2S_RX_CORE_CFG_OFFSET</a>))\</div>
<div class="line">          &amp; <a class="code" href="group__i2srx.html#ga6f0aaac08ca351e2389bbe04a8b6a87f">XI2S_RX_REG_CFG_NUM_CH_MASK</a>) &gt;&gt; <a class="code" href="group__i2srx.html#ga33b447ccf86e1d8e207cd5b04cc0e0bd">XI2S_RX_REG_CFG_NUM_CH_SHIFT</a>)</div>
<div class="ttc" id="group__i2srx_html_gaab2f8c799ff6de247d102de9eca1578c"><div class="ttname"><a href="group__i2srx.html#gaab2f8c799ff6de247d102de9eca1578c">XI2S_RX_CORE_CFG_OFFSET</a></div><div class="ttdeci">#define XI2S_RX_CORE_CFG_OFFSET</div><div class="ttdoc">Core Configuration Register. </div><div class="ttdef"><b>Definition:</b> xi2srx_hw.h:43</div></div>
<div class="ttc" id="group__i2srx_html_ga7f13e37d826cfd786b54f7ad04c0fd3c"><div class="ttname"><a href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a></div><div class="ttdeci">#define XI2s_Rx_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a XI2s Receiver register. </div><div class="ttdef"><b>Definition:</b> xi2srx_hw.h:170</div></div>
<div class="ttc" id="group__i2srx_html_ga33b447ccf86e1d8e207cd5b04cc0e0bd"><div class="ttname"><a href="group__i2srx.html#ga33b447ccf86e1d8e207cd5b04cc0e0bd">XI2S_RX_REG_CFG_NUM_CH_SHIFT</a></div><div class="ttdeci">#define XI2S_RX_REG_CFG_NUM_CH_SHIFT</div><div class="ttdoc">Maximum number of channels bit shift. </div><div class="ttdef"><b>Definition:</b> xi2srx_hw.h:71</div></div>
<div class="ttc" id="group__i2srx_html_ga6f0aaac08ca351e2389bbe04a8b6a87f"><div class="ttname"><a href="group__i2srx.html#ga6f0aaac08ca351e2389bbe04a8b6a87f">XI2S_RX_REG_CFG_NUM_CH_MASK</a></div><div class="ttdeci">#define XI2S_RX_REG_CFG_NUM_CH_MASK</div><div class="ttdoc">Maximum number of channels mask. </div><div class="ttdef"><b>Definition:</b> xi2srx_hw.h:73</div></div>
</div><!-- fragment -->
<p>This macro reads the maximum number of XI2s channels available. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Maximum number of XI2s Channels.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__i2srx.html#ga7b7e72e5a3a6b2d4cbddf5f41545c574" title="This macro reads the maximum number of XI2s channels available. ">XI2s_Rx_GetMaxChannels(XI2s_Rx *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__i2srx.html#ga8be6ac54842b054fb0f5b047669a794c">XI2s_Rx_SelfTest()</a>.</p>

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<a class="anchor" id="ga7089f6d78ab940b47ac4e63cc9de876d"></a>
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          <td class="memname">#define XI2S_RX_GINTR_EN_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga6ff2b2e7bc857175d47e3b396337c3c8">XI2S_RX_GINTR_EN_SHIFT</a>)</td>
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<p>Global Interrupt Enable mask. </p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>.</p>

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<a class="anchor" id="ga6ff2b2e7bc857175d47e3b396337c3c8"></a>
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          <td class="memname">#define XI2S_RX_GINTR_EN_SHIFT&#160;&#160;&#160;(31)</td>
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<p>Global Interrupt Enable bit shift. </p>

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<a class="anchor" id="ga09a5bac7db972eedb59f8a333b9ab962"></a>
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          <td class="memname">#define XI2s_Rx_In32&#160;&#160;&#160;Xil_In32</td>
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<p>Input Operations. </p>

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          <td class="memname">#define XI2S_RX_INTR_AES_BLKCMPLT_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gaeeff2f78e8d4799f14b13f5dd74f07ac">XI2S_RX_INTR_AES_BLKCMPLT_SHIFT</a>)</td>
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<p>AES Block Complete Interrupt mask. </p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>, and <a class="el" href="group__i2srx.html#gaca17a3387ef6bb0acdcfd20b94c0b7b1">XI2s_Rx_IntrHandler()</a>.</p>

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<a class="anchor" id="gaeeff2f78e8d4799f14b13f5dd74f07ac"></a>
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          <td class="memname">#define XI2S_RX_INTR_AES_BLKCMPLT_SHIFT&#160;&#160;&#160;(0)</td>
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<p>AES Block Complete Interrupt bit shift. </p>

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<a class="anchor" id="gacf7d542116f93c176f729165c0c0ab46"></a>
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          <td class="memname">#define XI2S_RX_INTR_AUDOVRFLW_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga12970ee31e47fcfe72564f65923519ff">XI2S_RX_INTR_AUDOVRFLW_SHIFT</a>)</td>
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<p>Audio Overflow Detected Interrupt mask. </p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>, and <a class="el" href="group__i2srx.html#gaca17a3387ef6bb0acdcfd20b94c0b7b1">XI2s_Rx_IntrHandler()</a>.</p>

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<a class="anchor" id="ga12970ee31e47fcfe72564f65923519ff"></a>
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          <td class="memname">#define XI2S_RX_INTR_AUDOVRFLW_SHIFT&#160;&#160;&#160;(1)</td>
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<p>Audio Overflow Detected Interrupt bit shift. </p>

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          <td class="memname">#define XI2S_RX_IRQCTRL_OFFSET&#160;&#160;&#160;0x10</td>
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<p>Interrupt Control Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga80556a73ef85dd5a4731afab9ad10f22">XI2s_Rx_IntrDisable()</a>, <a class="el" href="group__i2srx.html#ga595ca2872d1b5b59f05a229b3a28fd86">XI2s_Rx_IntrEnable()</a>, and <a class="el" href="group__i2srx.html#gaca17a3387ef6bb0acdcfd20b94c0b7b1">XI2s_Rx_IntrHandler()</a>.</p>

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          <td class="memname">#define XI2S_RX_IRQSTS_OFFSET&#160;&#160;&#160;0x14</td>
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<p>Interrupt Status Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#gaca17a3387ef6bb0acdcfd20b94c0b7b1">XI2s_Rx_IntrHandler()</a>.</p>

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          <td class="memname">#define XI2s_Rx_IsXI2sMaster</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, (<a class="code" href="group__i2srx.html#gaab2f8c799ff6de247d102de9eca1578c">XI2S_RX_CORE_CFG_OFFSET</a>))\</div>
<div class="line">          &amp; <a class="code" href="group__i2srx.html#gacc9bad93a6ce59caa98a961eca5180fd">XI2S_RX_REG_CFG_MSTR_MASK</a>) ? TRUE : FALSE)</div>
<div class="ttc" id="group__i2srx_html_gaab2f8c799ff6de247d102de9eca1578c"><div class="ttname"><a href="group__i2srx.html#gaab2f8c799ff6de247d102de9eca1578c">XI2S_RX_CORE_CFG_OFFSET</a></div><div class="ttdeci">#define XI2S_RX_CORE_CFG_OFFSET</div><div class="ttdoc">Core Configuration Register. </div><div class="ttdef"><b>Definition:</b> xi2srx_hw.h:43</div></div>
<div class="ttc" id="group__i2srx_html_ga7f13e37d826cfd786b54f7ad04c0fd3c"><div class="ttname"><a href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a></div><div class="ttdeci">#define XI2s_Rx_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a XI2s Receiver register. </div><div class="ttdef"><b>Definition:</b> xi2srx_hw.h:170</div></div>
<div class="ttc" id="group__i2srx_html_gacc9bad93a6ce59caa98a961eca5180fd"><div class="ttname"><a href="group__i2srx.html#gacc9bad93a6ce59caa98a961eca5180fd">XI2S_RX_REG_CFG_MSTR_MASK</a></div><div class="ttdeci">#define XI2S_RX_REG_CFG_MSTR_MASK</div><div class="ttdoc">Is XI2S Master mask. </div><div class="ttdef"><b>Definition:</b> xi2srx_hw.h:69</div></div>
</div><!-- fragment -->
<p>This macro returns the XI2s operating mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE : is XI2s Master</li>
<li>FALSE : is XI2s Slave</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__i2srx.html#gadf7ee99ef4ef8a11b48c8da71da0398b" title="This macro returns the XI2s operating mode. ">XI2s_Rx_IsXI2sMaster(XI2s_Rx *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__i2srx.html#ga8be6ac54842b054fb0f5b047669a794c">XI2s_Rx_SelfTest()</a>.</p>

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          <td class="memname">#define XI2S_RX_LOG_ITEM_BUFFER_SIZE&#160;&#160;&#160;(256)</td>
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<p>@ name Log Item Buffer Size </p>

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          <td class="memname">#define XI2s_Rx_Out32&#160;&#160;&#160;Xil_Out32</td>
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<p>Output Operations. </p>

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          <td class="memname">#define XI2s_Rx_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__i2srx.html#ga09a5bac7db972eedb59f8a333b9ab962">XI2s_Rx_In32</a>((BaseAddress) + ((u32)RegOffset))</td>
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<p>This macro reads a value from a XI2s Receiver register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the XI2s Receiver core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c" title="This macro reads a value from a XI2s Receiver register. ">XI2s_Rx_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__i2srx.html#ga3a853463222fc023817337626e04ea1a">XI2s_Rx_Enable()</a>, <a class="el" href="group__i2srx.html#ga80556a73ef85dd5a4731afab9ad10f22">XI2s_Rx_IntrDisable()</a>, <a class="el" href="group__i2srx.html#ga595ca2872d1b5b59f05a229b3a28fd86">XI2s_Rx_IntrEnable()</a>, <a class="el" href="group__i2srx.html#gaca17a3387ef6bb0acdcfd20b94c0b7b1">XI2s_Rx_IntrHandler()</a>, <a class="el" href="group__i2srx.html#ga68a5ca9532a69737b7d8788edd9f822d">XI2s_Rx_Justify()</a>, <a class="el" href="group__i2srx.html#ga4407276f62220e4983d6ec7251ad98d6">XI2s_Rx_JustifyEnable()</a>, and <a class="el" href="group__i2srx.html#gae745a449c173356fad2c4f4d3f19d9e0">XI2s_Rx_LatchAesChannelStatus()</a>.</p>

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          <td class="memname">#define XI2S_RX_REG_CFG_DWDTH_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga9cf777ebbfe32e3744fc3ec6e7b0b439">XI2S_RX_REG_CFG_DWDTH_SHIFT</a>)</td>
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<p>XI2S Data Width mask. </p>

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          <td class="memname">#define XI2S_RX_REG_CFG_DWDTH_SHIFT&#160;&#160;&#160;(16)</td>
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<p>XI2S Data Width bit shift. </p>

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          <td class="memname">#define XI2S_RX_REG_CFG_MSTR_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga386baab9d9d9e77e9569f78f8535c79a">XI2S_RX_REG_CFG_MSTR_SHIFT</a>)</td>
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      </table>
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<p>Is XI2S Master mask. </p>

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          <td class="memname">#define XI2S_RX_REG_CFG_MSTR_SHIFT&#160;&#160;&#160;(0)</td>
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<p>Is XI2S Master bit shift. </p>

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          <td class="memname">#define XI2S_RX_REG_CFG_NUM_CH_MASK&#160;&#160;&#160;(0xF &lt;&lt; XI2S_RX_REG_CFG_NUM_CH_SHIFT)</td>
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<p>Maximum number of channels mask. </p>

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          <td class="memname">#define XI2S_RX_REG_CFG_NUM_CH_SHIFT&#160;&#160;&#160;(8)</td>
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<p>Maximum number of channels bit shift. </p>

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          <td class="memname">#define XI2S_RX_REG_CHCTRL_CHMUX_MASK&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_RX_REG_CHCTRL_CHMUX_SHIFT)</td>
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<p>Channel MUX mask. </p>

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          <td class="memname">#define XI2S_RX_REG_CHCTRL_CHMUX_SHIFT&#160;&#160;&#160;(0)</td>
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<p>Channel MUX bit shift. </p>

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          <td class="memname">#define XI2S_RX_REG_CTRL_EN_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga2b6fec3d30ffb6d6e75686cbd6050d05">XI2S_RX_REG_CTRL_EN_SHIFT</a>)</td>
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<p>Module Enable mask. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga3a853463222fc023817337626e04ea1a">XI2s_Rx_Enable()</a>.</p>

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<p>Module Enable bit shift. </p>

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          <td class="memname">#define XI2S_RX_REG_CTRL_JFE_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gac9e9f8391850f0ca4407e7fda7b3c7d6">XI2S_RX_REG_CTRL_JFE_SHIFT</a>)</td>
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<p>Justification Enable or Disable mask. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga4407276f62220e4983d6ec7251ad98d6">XI2s_Rx_JustifyEnable()</a>.</p>

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          <td class="memname">#define XI2S_RX_REG_CTRL_JFE_SHIFT&#160;&#160;&#160;(1)</td>
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      </table>
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<p>Justification Enable or Disable shift. </p>

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          <td class="memname">#define XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga2a4b4b0ed331511eea0872abe6d1a008">XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT</a>)</td>
        </tr>
      </table>
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<p>Latch AES Channel Status mask. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#gae745a449c173356fad2c4f4d3f19d9e0">XI2s_Rx_LatchAesChannelStatus()</a>.</p>

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<p>Latch AES Channel Status bit shift. </p>

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          <td class="memname">#define XI2S_RX_REG_CTRL_LORJF_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gaf733f45be6a7f7c489c2ef5a0faf1cc1">XI2S_RX_REG_CTRL_LORJF_SHIFT</a>)</td>
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<p>Left or Right Justification mask. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga68a5ca9532a69737b7d8788edd9f822d">XI2s_Rx_Justify()</a>.</p>

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<p>Left or Right Justification shift. </p>

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          <td class="memname">#define XI2S_RX_REG_TMR_SCLKDIV_MASK&#160;&#160;&#160;(0xF &lt;&lt; XI2S_RX_REG_TMR_SCLKDIV_SHIFT)</td>
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<p>SClk Divider mask. </p>

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          <td class="memname">#define XI2S_RX_REG_TMR_SCLKDIV_SHIFT&#160;&#160;&#160;(0)</td>
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<p>SClk Divider bit shift. </p>

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          <td class="memname">#define XI2S_RX_TMR_CTRL_OFFSET&#160;&#160;&#160;0x20</td>
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<p>XI2S Timing Control Register. </p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga6b26d3fc18f6a8a65f2a55eb94300aac">XI2s_Rx_SetSclkOutDiv()</a>.</p>

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          <td class="memname">#define XI2s_Rx_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__i2srx.html#gadab8698c5b4c02161f42cfc947c5d1b2">XI2s_Rx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td>
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<p>This macro writes a value to a XI2s Receiver register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the XI2s Receiver core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f" title="This macro writes a value to a XI2s Receiver register. ">XI2s_Rx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__i2srx.html#ga700662592a50d2f7ee92aff8304706f3">XI2s_Rx_ClrAesChStatRegs()</a>, <a class="el" href="group__i2srx.html#ga3a853463222fc023817337626e04ea1a">XI2s_Rx_Enable()</a>, <a class="el" href="group__i2srx.html#ga80556a73ef85dd5a4731afab9ad10f22">XI2s_Rx_IntrDisable()</a>, <a class="el" href="group__i2srx.html#ga595ca2872d1b5b59f05a229b3a28fd86">XI2s_Rx_IntrEnable()</a>, <a class="el" href="group__i2srx.html#ga68a5ca9532a69737b7d8788edd9f822d">XI2s_Rx_Justify()</a>, <a class="el" href="group__i2srx.html#ga4407276f62220e4983d6ec7251ad98d6">XI2s_Rx_JustifyEnable()</a>, <a class="el" href="group__i2srx.html#gae745a449c173356fad2c4f4d3f19d9e0">XI2s_Rx_LatchAesChannelStatus()</a>, <a class="el" href="group__i2srx.html#ga0732ac9b13399678fe408cf55eeab264">XI2s_Rx_SetAesChStatus()</a>, <a class="el" href="group__i2srx.html#ga522d6260d91826f18572844fb0fbf39d">XI2s_Rx_SetChMux()</a>, and <a class="el" href="group__i2srx.html#ga6b26d3fc18f6a8a65f2a55eb94300aac">XI2s_Rx_SetSclkOutDiv()</a>.</p>

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<h2 class="groupheader">Typedef Documentation</h2>
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          <td class="memname">typedef void(* XI2s_Rx_Callback)(void *CallbackRef)</td>
        </tr>
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<p>Callback function data type for handling interrupt requests from the XI2s Receiver peripheral. </p>
<p>The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler is called in an interrupt context such that minimal processing should be performed.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallBackRef</td><td>is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

</div>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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          <td class="memname">enum <a class="el" href="group__i2srx.html#ga29fe382428db32ed7ad00cd1082609e2">XI2s_Rx_ChannelId</a></td>
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<p>These constants specify different channel ID's. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga29fe382428db32ed7ad00cd1082609e2a0d5df5d0173cff1b2ddfda530698d4d6"></a>XI2S_RX_CHID0</em>&nbsp;</td><td class="fielddoc">
<p>Channel 0. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga29fe382428db32ed7ad00cd1082609e2aa4e1404437e2db8108a9b6da4ba5fd03"></a>XI2S_RX_CHID1</em>&nbsp;</td><td class="fielddoc">
<p>Channel 1. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga29fe382428db32ed7ad00cd1082609e2ae0fcdcc15c32a53bd6b7e907cbc89e6a"></a>XI2S_RX_CHID2</em>&nbsp;</td><td class="fielddoc">
<p>Channel 2. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga29fe382428db32ed7ad00cd1082609e2aec3f40e4bcd10c6af7fbbf987a89e4db"></a>XI2S_RX_CHID3</em>&nbsp;</td><td class="fielddoc">
<p>Channel 3. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga29fe382428db32ed7ad00cd1082609e2a3c8607ad2a5133fa10d64bbcf6c37e20"></a>XI2S_RX_NUM_CHANNELS</em>&nbsp;</td><td class="fielddoc">
<p>Number of Channel ID's. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="group__i2srx.html#gace941535376f24ef90b44f160f55b70e">XI2s_Rx_ChMuxInput</a></td>
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<p>This typedef specifies the input sources of the the XI2s Receiver. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggace941535376f24ef90b44f160f55b70eaabeb21056fc06cd622d7a0b191a0127e"></a>XI2S_RX_CHMUX_DISABLED</em>&nbsp;</td><td class="fielddoc">
<p>Channel disabled. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggace941535376f24ef90b44f160f55b70ea0df7f22d4a2d5f2f1dbf9305443194e1"></a>XI2S_RX_CHMUX_XI2S_01</em>&nbsp;</td><td class="fielddoc">
<p>XI2S Audio Channel 0 and 1. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggace941535376f24ef90b44f160f55b70ea269c4b47b2a78c065aee963d3396aab2"></a>XI2S_RX_CHMUX_XI2S_23</em>&nbsp;</td><td class="fielddoc">
<p>XI2S Audio Channel 2 and 3. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggace941535376f24ef90b44f160f55b70ea55bc0f78e50439c70f6a2580471a4b3b"></a>XI2S_RX_CHMUX_XI2S_45</em>&nbsp;</td><td class="fielddoc">
<p>XI2S Audio Channel 4 and 5. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggace941535376f24ef90b44f160f55b70ea51c18d250475c4f196015e8972e44b1f"></a>XI2S_RX_CHMUX_XI2S_67</em>&nbsp;</td><td class="fielddoc">
<p>XI2S Audio Channel 6 and 7. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggace941535376f24ef90b44f160f55b70ea4f5885668f79e682e8ffa887330e99de"></a>XI2S_RX_CHMUX_WAVEGEN</em>&nbsp;</td><td class="fielddoc">
<p>Wave Generator. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="group__i2srx.html#ga73cea697b9b2b7edb411ac4ecf01b349">XI2s_Rx_HandlerType</a></td>
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<p>These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga73cea697b9b2b7edb411ac4ecf01b349ad5a32351d829855baf3f691a3718d176"></a>XI2S_RX_HANDLER_AES_BLKCMPLT</em>&nbsp;</td><td class="fielddoc">
<p>AES Block Complete Handler. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga73cea697b9b2b7edb411ac4ecf01b349adbc31f3ef63cffa075c18ad2a1288b0d"></a>XI2S_RX_HANDLER_AUD_OVRFLW</em>&nbsp;</td><td class="fielddoc">
<p>Audio Overflow Detected Handler. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga73cea697b9b2b7edb411ac4ecf01b349a743f017dc379e345fa2511aa81fc3621"></a>XI2S_RX_NUM_HANDLERS</em>&nbsp;</td><td class="fielddoc">
<p>Number of handler types. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="group__i2srx.html#ga787bbfc7c06021fa68c40dd4e1248ec1">XI2s_Rx_Justification</a></td>
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<p>This typedef specifies the justification of the the XI2s Receiver. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga787bbfc7c06021fa68c40dd4e1248ec1aa461181648e4f912e5f6bf33b922dae8"></a>XI2S_RX_JUSTIFY_LEFT</em>&nbsp;</td><td class="fielddoc">
<p>Left Justification is enabled. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga787bbfc7c06021fa68c40dd4e1248ec1a9bd0f58e092109daff42c8007ef31110"></a>XI2S_RX_JUSTIFY_RIGHT</em>&nbsp;</td><td class="fielddoc">
<p>Right Justification is enabled. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="group__i2srx.html#ga4fecc6c86b725108f3488292d518816c">XI2s_Rx_LogEvt</a></td>
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<p>These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga4fecc6c86b725108f3488292d518816cafcbc177f865f01745336004358d4479e"></a>XI2S_RX_AES_BLKCMPLT_EVT</em>&nbsp;</td><td class="fielddoc">
<p>AES Block Complete Event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga4fecc6c86b725108f3488292d518816caac11c46eda786e90c37a6bc1dac96897"></a>XI2S_RX_AUD_OVERFLOW_EVT</em>&nbsp;</td><td class="fielddoc">
<p>Audio Overflow Detected Event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga4fecc6c86b725108f3488292d518816cabd013a083c7841b935a6f5f5d38d45a5"></a>XI2S_RX_LOG_EVT_INVALID</em>&nbsp;</td><td class="fielddoc">
<p>Invalid Log Event. </p>
</td></tr>
</table>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">int XI2s_Rx_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_i2srx___config.html">XI2srx_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function initializes the XI2s Receiver. </p>
<p>This function must be called prior to using the core. Initialization of the XI2s Receiver includes setting up the instance data, and ensuring the hardware is in a quiescent state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>points to the configuration structure associated with the XI2s Receiver. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS : if successful.</li>
<li>XST_FAILURE : if version mismatched.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="struct_x_i2s___rx.html#af37339d572a56a98e696f0dec19b0c74">XI2s_Rx::IsReady</a>, <a class="el" href="group__i2srx.html#ga3a853463222fc023817337626e04ea1a">XI2s_Rx_Enable()</a>, and <a class="el" href="group__i2srx.html#ga8be6ac54842b054fb0f5b047669a794c">XI2s_Rx_SelfTest()</a>.</p>

<p>Referenced by <a class="el" href="xi2srx__selftest__example_8c.html#ad83c13604fe5e0b654b169df04ba2c0b">I2srx_SelfTest_Example()</a>, <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>, and <a class="el" href="group__i2srx.html#ga164f49a595611f6092889fbc157982f4">XI2s_Rx_Initialize()</a>.</p>

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          <td class="memname">void XI2s_Rx_ClrAesChStatRegs </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function clears the captured AES Channel Status bits. </p>
<p>This will clear all the 6 channel status registers.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__i2srx.html#gaef854c082d18fb31d75d15c23aa7fab5">XI2S_RX_AES_CHSTS0_OFFSET</a>, <a class="el" href="group__i2srx.html#ga6eb6685030ce7a4097e2d26591026109">XI2S_RX_AES_CHSTS1_OFFSET</a>, <a class="el" href="group__i2srx.html#ga4a5e64ec439b371f7dbb7795796ea525">XI2S_RX_AES_CHSTS2_OFFSET</a>, <a class="el" href="group__i2srx.html#ga5aec8ad439da8047b7e2406680091bb3">XI2S_RX_AES_CHSTS3_OFFSET</a>, <a class="el" href="group__i2srx.html#ga64228e861649cfca19122186738890c3">XI2S_RX_AES_CHSTS4_OFFSET</a>, <a class="el" href="group__i2srx.html#gada5ad0f01fc6b245bc58fb0ac66f3672">XI2S_RX_AES_CHSTS5_OFFSET</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Rx_Enable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Enable</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function enables/disables the XI2s Receiver. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance. </td></tr>
    <tr><td class="paramname">Enable</td><td>specifies TRUE/FALSE value to either enable or disable the XI2s Receiver.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="struct_x_i2s___rx.html#a03429754d7904790001a12c6ab28877f">XI2s_Rx::IsStarted</a>, <a class="el" href="group__i2srx.html#gaa79a92debd04aa3b8f9866869fcee2ea">XI2S_RX_CORE_CTRL_OFFSET</a>, <a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>, <a class="el" href="group__i2srx.html#ga72d3a8ea524c40940140512a982fb910">XI2S_RX_REG_CTRL_EN_MASK</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>, and <a class="el" href="group__i2srx.html#ga4d444eaa5a0dd7d980c0d216b3382260">XI2s_Rx_CfgInitialize()</a>.</p>

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          <td class="memname">int XI2s_Rx_Initialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Initializes a specific <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance such that the driver is ready to use. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">DeviceId</td><td>is the unique id of the device controlled by this <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance. Passing in a device id associates the generic <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance to a specific device, as chosen by the caller or application developer.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful.</li>
<li>XST_DEVICE_NOT_FOUND if the device was not found in the configuration such that initialization could not be accomplished.</li>
<li>XST_INVALID_VERSION if version mismatched </li>
</ul>
</dd></dl>

<p>References <a class="el" href="group__i2srx.html#ga4d444eaa5a0dd7d980c0d216b3382260">XI2s_Rx_CfgInitialize()</a>, and <a class="el" href="group__i2srx.html#ga86fad2b52bbb42c12f21c72463a614b5">XI2s_Rx_LookupConfig()</a>.</p>

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          <td class="memname">void XI2s_Rx_IntrDisable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function disables the specified interrupt of the XI2s Receiver. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance. </td></tr>
    <tr><td class="paramname">Mask</td><td>is a bit mask of the interrupts to be disabled.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section see"><dt>See Also</dt><dd>XI2s_Receiver_HW for the available interrupt masks. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="group__i2srx.html#ga9d9730105131e980b1b2ca3996969f31">XI2S_RX_IRQCTRL_OFFSET</a>, <a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Rx_IntrEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function enables the specified interrupt of the XI2s Receiver. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance. </td></tr>
    <tr><td class="paramname">Mask</td><td>is a bit mask of the interrupts to be enabled.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section see"><dt>See Also</dt><dd>XI2srx_HW for the available interrupt masks. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="group__i2srx.html#ga9d9730105131e980b1b2ca3996969f31">XI2S_RX_IRQCTRL_OFFSET</a>, <a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>.</p>

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          <td class="memname">void XI2s_Rx_IntrHandler </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function is the interrupt handler for the XI2s Receiver driver. </p>
<p>This handler reads the pending interrupt from the XI2s Receiver peripheral, determines the source of the interrupts, clears the interrupts and calls callbacks accordingly.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a0e284b134511282b0e3402dc679b057d">XI2s_Rx::AudOverflowHandler</a>, <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="struct_x_i2s___rx.html#af37339d572a56a98e696f0dec19b0c74">XI2s_Rx::IsReady</a>, <a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816cafcbc177f865f01745336004358d4479e">XI2S_RX_AES_BLKCMPLT_EVT</a>, <a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816caac11c46eda786e90c37a6bc1dac96897">XI2S_RX_AUD_OVERFLOW_EVT</a>, <a class="el" href="group__i2srx.html#gafa37ac42887b7ca3d17a5a48af43c3d1">XI2S_RX_INTR_AES_BLKCMPLT_MASK</a>, <a class="el" href="group__i2srx.html#gacf7d542116f93c176f729165c0c0ab46">XI2S_RX_INTR_AUDOVRFLW_MASK</a>, <a class="el" href="group__i2srx.html#ga9d9730105131e980b1b2ca3996969f31">XI2S_RX_IRQCTRL_OFFSET</a>, <a class="el" href="group__i2srx.html#ga10ebd12832c0df2b25d86e1c426917a2">XI2S_RX_IRQSTS_OFFSET</a>, <a class="el" href="group__i2srx.html#gad797c77106bcc4da0a72e65e5620fa02">XI2s_Rx_LogWrite()</a>, and <a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>.</p>

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          <td class="memname">void XI2s_Rx_Justify </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2srx.html#ga787bbfc7c06021fa68c40dd4e1248ec1">XI2s_Rx_Justification</a>&#160;</td>
          <td class="paramname"><em>Justify</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function is to enable right/left justification. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance. </td></tr>
    <tr><td class="paramname">Justify</td><td>is a enum to select the left or right justfication.<ul>
<li>XI2S_RX_JUSTIFY_LEFT : Left justication</li>
<li>XI2S_RX_JUSTIFY_RIGHT : Right justification</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="group__i2srx.html#gaa79a92debd04aa3b8f9866869fcee2ea">XI2S_RX_CORE_CTRL_OFFSET</a>, <a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>, <a class="el" href="group__i2srx.html#gae1e05f03cc894aaa4e5bf213460eeb43">XI2S_RX_REG_CTRL_LORJF_MASK</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Rx_JustifyEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Enable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function enables/disables the justification. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance. </td></tr>
    <tr><td class="paramname">Enable</td><td>specifies TRUE/FALSE value to either enable or disable the justification.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="group__i2srx.html#gaa79a92debd04aa3b8f9866869fcee2ea">XI2S_RX_CORE_CTRL_OFFSET</a>, <a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>, <a class="el" href="group__i2srx.html#ga4bed9d26f96c101a80fdeb5e16c61882">XI2S_RX_REG_CTRL_JFE_MASK</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Rx_LatchAesChannelStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function requests the XI2s Receiver to latch the AES Channel Status bits from the registers. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="group__i2srx.html#gaa79a92debd04aa3b8f9866869fcee2ea">XI2S_RX_CORE_CTRL_OFFSET</a>, <a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>, <a class="el" href="group__i2srx.html#gab1cb52ffff197179ecb2453f3b055f2e">XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Rx_LogDisplay </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function prints the contents of the logging buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="struct_x_i2srx___config.html#abeb8d74491f431d6f01e4e1361790f00">XI2srx_Config::DeviceId</a>, <a class="el" href="struct_x_i2s___rx___log_item.html#a4c0af844eba3d12af2d8519c5cc6aa1e">XI2s_Rx_LogItem::Event</a>, <a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816cafcbc177f865f01745336004358d4479e">XI2S_RX_AES_BLKCMPLT_EVT</a>, <a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816caac11c46eda786e90c37a6bc1dac96897">XI2S_RX_AUD_OVERFLOW_EVT</a>, <a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816cabd013a083c7841b935a6f5f5d38d45a5">XI2S_RX_LOG_EVT_INVALID</a>, and <a class="el" href="group__i2srx.html#gace02e57eaf489fffb38e0f3d4f69c8d3">XI2s_Rx_LogRead()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_i2s___rx___log_item.html">XI2s_Rx_LogItem</a> * XI2s_Rx_LogRead </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function returns the next item in the logging buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>When the buffer is filled, the next log item is returned. When the buffer is empty, NULL is returned. </dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx___log.html#af4a0ae28aae0f9c715d1c31a86e8775c">XI2s_Rx_Log::Head</a>, <a class="el" href="struct_x_i2s___rx___log.html#afce10615c31d774e63fe22e99bda4636">XI2s_Rx_Log::Items</a>, <a class="el" href="struct_x_i2s___rx.html#a2fa74be2c52efa0a8e2c73a612b57f0c">XI2s_Rx::Log</a>, and <a class="el" href="struct_x_i2s___rx___log.html#ae4d081a816f800aa7c7032cedc1822bb">XI2s_Rx_Log::Tail</a>.</p>

<p>Referenced by <a class="el" href="group__i2srx.html#gad30090fdf63b203192a837ca5860992b">XI2s_Rx_LogDisplay()</a>.</p>

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          <td class="memname">void XI2s_Rx_LogReset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function clears the contents of the logging buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx___log.html#af4a0ae28aae0f9c715d1c31a86e8775c">XI2s_Rx_Log::Head</a>, <a class="el" href="struct_x_i2s___rx___log.html#a49948767f4b2b4240b4785f1b38f30c1">XI2s_Rx_Log::IsEnabled</a>, <a class="el" href="struct_x_i2s___rx.html#a2fa74be2c52efa0a8e2c73a612b57f0c">XI2s_Rx::Log</a>, and <a class="el" href="struct_x_i2s___rx___log.html#ae4d081a816f800aa7c7032cedc1822bb">XI2s_Rx_Log::Tail</a>.</p>

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          <td class="memname">void XI2s_Rx_LogWrite </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2srx.html#ga4fecc6c86b725108f3488292d518816c">XI2s_Rx_LogEvt</a>&#160;</td>
          <td class="paramname"><em>Event</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function writes XI2s Receiver logs into the buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance. </td></tr>
    <tr><td class="paramname">Event</td><td>is the log event type. </td></tr>
    <tr><td class="paramname">Data</td><td>is the log data.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Log write is done only if the log is enabled. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx___log_item.html#a209f66c283495774513f9745e91e05d3">XI2s_Rx_LogItem::Data</a>, <a class="el" href="struct_x_i2s___rx___log_item.html#a4c0af844eba3d12af2d8519c5cc6aa1e">XI2s_Rx_LogItem::Event</a>, <a class="el" href="struct_x_i2s___rx___log.html#af4a0ae28aae0f9c715d1c31a86e8775c">XI2s_Rx_Log::Head</a>, <a class="el" href="struct_x_i2s___rx___log.html#a49948767f4b2b4240b4785f1b38f30c1">XI2s_Rx_Log::IsEnabled</a>, <a class="el" href="struct_x_i2s___rx___log.html#afce10615c31d774e63fe22e99bda4636">XI2s_Rx_Log::Items</a>, <a class="el" href="struct_x_i2s___rx.html#a2fa74be2c52efa0a8e2c73a612b57f0c">XI2s_Rx::Log</a>, <a class="el" href="struct_x_i2s___rx___log.html#ae4d081a816f800aa7c7032cedc1822bb">XI2s_Rx_Log::Tail</a>, and <a class="el" href="group__i2srx.html#gga4fecc6c86b725108f3488292d518816cabd013a083c7841b935a6f5f5d38d45a5">XI2S_RX_LOG_EVT_INVALID</a>.</p>

<p>Referenced by <a class="el" href="group__i2srx.html#gaca17a3387ef6bb0acdcfd20b94c0b7b1">XI2s_Rx_IntrHandler()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_i2srx___config.html">XI2srx_Config</a> * XI2s_Rx_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p>This function returns a reference to an <a class="el" href="struct_x_i2srx___config.html" title="This typedef contains configuration information for the XI2s Receiver. ">XI2srx_Config</a> structure based on the core id, <em>DeviceId</em>. </p>
<p>The return value will refer to an entry in the device configuration table defined in the xi2srx_g.c file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique core ID of the XI2s Receiver core for the lookup operation.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>returns a reference to a config record in the configuration table corresponding to <em>DeviceId</em>, or NULL if no match is found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xi2srx__selftest__example_8c.html#ad83c13604fe5e0b654b169df04ba2c0b">I2srx_SelfTest_Example()</a>, <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>, and <a class="el" href="group__i2srx.html#ga164f49a595611f6092889fbc157982f4">XI2s_Rx_Initialize()</a>.</p>

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          <td class="memname">int XI2s_Rx_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>Runs a self-test on the driver/device. </p>
<p>The self-test reads the version register, data width , max channels, Master or slave configuration and verifies the values</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful i.e. if the self test passes.</li>
<li>XST_FAILURE if unsuccessful i.e. if the self test fails</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__i2srx.html#ga7b7e72e5a3a6b2d4cbddf5f41545c574">XI2s_Rx_GetMaxChannels</a>, and <a class="el" href="group__i2srx.html#gadf7ee99ef4ef8a11b48c8da71da0398b">XI2s_Rx_IsXI2sMaster</a>.</p>

<p>Referenced by <a class="el" href="group__i2srx.html#ga4d444eaa5a0dd7d980c0d216b3382260">XI2s_Rx_CfgInitialize()</a>.</p>

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          <td class="memname">void XI2s_Rx_SetAesChStat </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>I2srx_SrcBuf</em>[], </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>I2srx_DstBuf</em>[]&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function reads the source buffer and writes to a destination buffer. </p>
<p>Before calling this API user application should write 192 bits i.e. 24 bytes to the array I2srx_SrcBuf. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">I2srx_SrcBuf</td><td>is the source buffer which has 192 channel status bits. </td></tr>
    <tr><td class="paramname">I2srx_DstBuf</td><td>is the destination buffer to store the 24 bytes.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>void. </dd></dl>
<p>&lt; use of channel status block</p>
<p>&lt; linear PCM identification</p>
<p>&lt; audio signal Pre-emphasis</p>
<p>&lt; lock indication</p>
<p>&lt; sampling frequency</p>
<p>&lt; channel mode</p>
<p>&lt; user bits management</p>
<p>&lt; use of auxiliary sample bits</p>
<p>&lt; source word length</p>
<p>&lt; indication of alignment level</p>
<p>&lt; channel mode</p>
<p>&lt; Channel number 0</p>
<p>&lt; Channel number 1</p>
<p>&lt; multi channel1 mode number</p>
<p>&lt; digital audio reference signal</p>
<p>&lt; reserved but undefined</p>
<p>&lt; sampling frequency</p>
<p>&lt; sampling frequency scaling flag</p>
<p>&lt; reserved but undefined</p>
<p>&lt; Alphanumeric channel origin data</p>
<p>&lt; Alphanumeric channel destination data</p>
<p>&lt; Local sample address code</p>
<p>&lt; Time-of-day sample address code</p>
<p>&lt; Reliability flags</p>
<p>&lt; Cyclic redundancy check character </p>

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          <td class="memname">void XI2s_Rx_SetAesChStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>AesChStatusBuf</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function sets the AES Channel Status bits to insert. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance. </td></tr>
    <tr><td class="paramname">AesChStatusBuf</td><td>is a pointer to a buffer containing the AES channel status bits.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="group__i2srx.html#gaef854c082d18fb31d75d15c23aa7fab5">XI2S_RX_AES_CHSTS0_OFFSET</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2srx.html#ga29fe382428db32ed7ad00cd1082609e2">XI2s_Rx_ChannelId</a>&#160;</td>
          <td class="paramname"><em>ChID</em>, </td>
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        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2srx.html#gace941535376f24ef90b44f160f55b70e">XI2s_Rx_ChMuxInput</a>&#160;</td>
          <td class="paramname"><em>InputSource</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function sets the input source for the specified AXI-Stream channel pair. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Receiver instance. </td></tr>
    <tr><td class="paramname">ChID</td><td>specifies the AXI-Stream channel pair<ul>
<li>0 : AXI-Stream channel 0 and 1</li>
<li>1 : AXI-Stream channel 2 and 3</li>
<li>2 : AXI-Stream channel 4 and 5</li>
<li>3 : AXI-Stream channel 6 and 7 </li>
</ul>
</td></tr>
    <tr><td class="paramname">InputSource</td><td>specifies the input source</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS : if successful.</li>
<li>XST_FAILURE : if the AXI-Stream channel pair is invalid. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="group__i2srx.html#gacc668d400426098bae3149a9fc4c094f">XI2S_RX_CH01_OFFSET</a>, <a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea4f5885668f79e682e8ffa887330e99de">XI2S_RX_CHMUX_WAVEGEN</a>, <a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea0df7f22d4a2d5f2f1dbf9305443194e1">XI2S_RX_CHMUX_XI2S_01</a>, <a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea269c4b47b2a78c065aee963d3396aab2">XI2S_RX_CHMUX_XI2S_23</a>, <a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea55bc0f78e50439c70f6a2580471a4b3b">XI2S_RX_CHMUX_XI2S_45</a>, <a class="el" href="group__i2srx.html#ggace941535376f24ef90b44f160f55b70ea51c18d250475c4f196015e8972e44b1f">XI2S_RX_CHMUX_XI2S_67</a>, <a class="el" href="group__i2srx.html#gga29fe382428db32ed7ad00cd1082609e2a3c8607ad2a5133fa10d64bbcf6c37e20">XI2S_RX_NUM_CHANNELS</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>.</p>

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          <td class="memname">int XI2s_Rx_SetHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2srx.html#ga73cea697b9b2b7edb411ac4ecf01b349">XI2s_Rx_HandlerType</a>&#160;</td>
          <td class="paramname"><em>HandlerType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2srx.html#gaef13cc9c4d09dc05e1027c43bc2aeed2">XI2s_Rx_Callback</a>&#160;</td>
          <td class="paramname"><em>FuncPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallbackRef</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function installs an asynchronous callback function for the given HandlerType: </p>
<pre>
HandlerType                              Callback Function
--------------------------------         ----------------------------------
(XI2S_RX_HANDLER_AES_BLKCMPLT)            AesBlkCmpltHandler
(XI2S_RX_HANDLER_AUD_OVERFLOW)            AudOverflowHandler
</pre><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___rx.html" title="The XI2s Receiver driver instance data. ">XI2s_Rx</a> core instance. </td></tr>
    <tr><td class="paramname">HandlerType</td><td>specifies the type of handler. </td></tr>
    <tr><td class="paramname">FuncPtr</td><td>is a pointer to the callback function. </td></tr>
    <tr><td class="paramname">CallbackRef</td><td>is a reference pointer passed on actual calling of the callback function.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if callback function installed successfully.</li>
<li>XST_INVALID_PARAM when HandlerType is invalid.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Invoking this function for a handler that already has been installed replaces it with the new handler. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a0e284b134511282b0e3402dc679b057d">XI2s_Rx::AudOverflowHandler</a>, <a class="el" href="group__i2srx.html#gga73cea697b9b2b7edb411ac4ecf01b349ad5a32351d829855baf3f691a3718d176">XI2S_RX_HANDLER_AES_BLKCMPLT</a>, <a class="el" href="group__i2srx.html#gga73cea697b9b2b7edb411ac4ecf01b349adbc31f3ef63cffa075c18ad2a1288b0d">XI2S_RX_HANDLER_AUD_OVRFLW</a>, and <a class="el" href="group__i2srx.html#gga73cea697b9b2b7edb411ac4ecf01b349a743f017dc379e345fa2511aa81fc3621">XI2S_RX_NUM_HANDLERS</a>.</p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>.</p>

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          <td class="memname">u32 XI2s_Rx_SetSclkOutDiv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___rx.html">XI2s_Rx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>MClk</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Fs</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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      </table>
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<p>This function calculates the SCLK Output divider value of the I2s timing generator. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the I2s Receiver instance. </td></tr>
    <tr><td class="paramname">MClk</td><td>is the frequency of the MClk. </td></tr>
    <tr><td class="paramname">Fs</td><td>is the sampling frequency of the system. Divider value for the SCLK generation MCLK/SCLK = SCLKOUT_DIV x 2 i.e. MCLK = 384xFs, SCLK = 48xFs (2x24bits) -&gt; SCLKOUT_DIV = MCLK/SCLK/2 = 4 Valid values are 1 through 15.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>- XST_FAILURE if SCLK Output divider is not calculated to be a positive integer.<ul>
<li>XST_SUCCESS, otherwise. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_i2s___rx.html#a7657d091fcc3dd42b0a8d86a1713b18f">XI2s_Rx::Config</a>, <a class="el" href="struct_x_i2srx___config.html#ac8287c82083c51bbb50169ccfc112504">XI2srx_Config::DWidth</a>, <a class="el" href="group__i2srx.html#gad10e1d11d2c50b2111dd3f8a4dd26389">XI2S_RX_TMR_CTRL_OFFSET</a>, and <a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi2srx__intr__example_8c.html#abda2a9bf51004e4536e4f737e898786a">I2sRxIntrExample()</a>.</p>

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